/* Freescale Enhanced Local Bus Controller FCM NAND driver
 *
 * Copyright (c) 2006-2008 Freescale Semiconductor
 *
 * Authors: Nick Spence <nick.spence@freescale.com>,
 *          Scott Wood <scottwood@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <tickLib.h>

#include "mpc83xx.h"
#include "MPC8313ERDB.h"
#include "immap_83xx.h"
#include "io.h"

#undef NAND_DEBUG

#ifdef NAND_DEBUG
#define DEBUG_ELBC
#define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
#else
#define vdbg(format, arg...) do {} while (0)
#endif

/* Can't use plain old DEBUG because the linux mtd
 * headers define it as a macro.
 */
#ifdef DEBUG_ELBC
#define dbg(format, arg...) printf("DEBUG: " format, ##arg)
#else
#define dbg(format, arg...) do {} while (0)
#endif

#define NAND_BANK	3
#define NAND_LARGE_PAGE	1
#define NAND_CHIP_SIZE	0x20000000	/* 512M */
#define NAND_PAGE_SIZE	2048
#define NAND_OOB_SIZE	64
#define NAND_PAGES_PER_BLOCK	64
#define NAND_BLOCK_SIZE	(NAND_PAGES_PER_BLOCK*NAND_PAGE_SIZE)
#define NAND_BLOCK_SHIFT	6
#define NAND_VBASE	0xC0000000

#define MAX_BANKS 4
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
#define FCM_TIMEOUT_MSECS 20 /* Maximum number of mSecs to wait for FCM */

#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)


/*
 * Standard NAND flash commands
 */
#define NAND_CMD_READ0		0
#define NAND_CMD_READ1		1
#define NAND_CMD_RNDOUT		5
#define NAND_CMD_PAGEPROG	0x10
#define NAND_CMD_READOOB	0x50
#define NAND_CMD_ERASE1		0x60
#define NAND_CMD_STATUS		0x70
#define NAND_CMD_STATUS_MULTI	0x71
#define NAND_CMD_SEQIN		0x80
#define NAND_CMD_RNDIN		0x85
#define NAND_CMD_READID		0x90
#define NAND_CMD_ERASE2		0xd0
#define NAND_CMD_RESET		0xff

/* Extended commands for large page devices */
#define NAND_CMD_READSTART	0x30
#define NAND_CMD_RNDOUTSTART	0xE0
#define NAND_CMD_CACHEDPROG	0x15


/* Status bits */
#define NAND_STATUS_FAIL	0x01
#define NAND_STATUS_FAIL_N1	0x02
#define NAND_STATUS_TRUE_READY	0x20
#define NAND_STATUS_READY	0x40
#define NAND_STATUS_WP		0x80


/* overview of the fsl elbc controller */

struct fsl_elbc_ctrl {
	/* device info */
	volatile lbus83xx_t *regs;
	volatile unsigned char *addr;        /* Address of assigned FCM buffer        */
	unsigned int page;       /* Last page written to / read from      */
	unsigned int read_bytes; /* Number of bytes read during command   */
	unsigned int column;     /* Saved column from SEQIN               */
	unsigned int index;      /* Pointer to next byte to 'read'        */
	unsigned int status;     /* status read from LTESR after last op  */
	unsigned int mdr;        /* UPM/FCM Data Register value           */
	unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
	unsigned int oob;        /* Non zero if operating on OOB data     */
	unsigned char *oob_poi;		/* Place to write ECC after read back    */
	unsigned char *data_poi;		/* Data buffer */
} elbc_ctrl;


extern int sysClkRateGet(void);
extern void sysMpc8308MsDelay (UINT mSeconds);

/*=================================*/

/*
 * Set up the FCM hardware block and page address fields, and the fcm
 * structure addr field to point to the correct FCM buffer in memory
 */
static void set_addr(struct fsl_elbc_ctrl *ctrl, int column, int page_addr, int oob)
{
	volatile lbus83xx_t *lbc = ctrl->regs;
	int buf_num;

	ctrl->page = page_addr;

	if (NAND_LARGE_PAGE) {
		out_be32(&lbc->fbar, page_addr >> 6);
		out_be32(&lbc->fpar,
			 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
			 (oob ? FPAR_LP_MS : 0) | column);
		buf_num = (page_addr & 1) << 2;
	} else {
		out_be32(&lbc->fbar, page_addr >> 5);
		out_be32(&lbc->fpar,
			 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
			 (oob ? FPAR_SP_MS : 0) | column);
		buf_num = page_addr & 7;
	}

	ctrl->addr = (unsigned char *)NAND_VBASE + buf_num * 1024;
	ctrl->index = column;

	/* for OOB data point to the second half of the buffer */
	if (oob)
		ctrl->index += NAND_LARGE_PAGE ? 2048 : 512;

	vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
	     "index %x\n",
	     buf_num, ctrl->addr, NAND_VBASE, ctrl->index);
}

/*
 * execute FCM command and wait for it to complete
 */
static int fsl_elbc_run_command(struct fsl_elbc_ctrl *ctrl)
{
	volatile lbus83xx_t *lbc = ctrl->regs;
	long long end_tick;
	unsigned int ltesr;

	/* Setup the FMR[OP] to execute without write protection */
	out_be32(&lbc->fmr, lbc->fmr | 3);
	if (ctrl->use_mdr)
		out_be32(&lbc->mdr, ctrl->mdr);

	vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
	     in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
	vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
	     "fbcr=%08x bank=%d\n",
	     in_be32(&lbc->fbar), in_be32(&lbc->fpar),
	     in_be32(&lbc->fbcr), NAND_BANK);

	/* execute special operation */
	out_be32(&lbc->lsor, NAND_BANK);

	/* wait for FCM complete flag or timeout */
	end_tick = (FCM_TIMEOUT_MSECS * 1000)/sysClkRateGet() + tickGet();

	ltesr = 0;
	while (end_tick > tickGet()) {
		ltesr = in_be32(&lbc->ltesr);
		if (ltesr & LTESR_CC)
			break;
	}

	ctrl->status = ltesr & LTESR_NAND_MASK;
	out_be32(&lbc->ltesr, ctrl->status);
	out_be32(&lbc->lteatr, 0);

	/* store mdr value in case it was needed */
	if (ctrl->use_mdr)
		ctrl->mdr = in_be32(&lbc->mdr);

	ctrl->use_mdr = 0;

	vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
	     ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));

	/* returns 0 on success otherwise non-zero) */
	return ctrl->status == LTESR_CC ? 0 : -1;
}

static void fsl_elbc_do_read(struct fsl_elbc_ctrl *ctrl, int oob)
{
	volatile lbus83xx_t *lbc = ctrl->regs;

	if (NAND_LARGE_PAGE) {
		out_be32(&lbc->fir,
			 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
			 (FIR_OP_CA  << FIR_OP1_SHIFT) |
			 (FIR_OP_PA  << FIR_OP2_SHIFT) |
			 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
			 (FIR_OP_RBW << FIR_OP4_SHIFT));

		out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
				    (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
	} else {
		out_be32(&lbc->fir,
			 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
			 (FIR_OP_CA  << FIR_OP1_SHIFT) |
			 (FIR_OP_PA  << FIR_OP2_SHIFT) |
			 (FIR_OP_RBW << FIR_OP3_SHIFT));

		if (oob)
			out_be32(&lbc->fcr,
				 NAND_CMD_READOOB << FCR_CMD0_SHIFT);
		else
			out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
	}
}

/* cmdfunc send commands to the FCM */
static void fsl_elbc_cmdfunc(struct fsl_elbc_ctrl *ctrl, unsigned int command,
			     int column, int page_addr)
{
	volatile lbus83xx_t *lbc = ctrl->regs;

	ctrl->use_mdr = 0;

	/* clear the read buffer */
	ctrl->read_bytes = 0;
	if (command != NAND_CMD_PAGEPROG)
		ctrl->index = 0;

	switch (command) {
	/* READ0 and READ1 read the entire buffer to use hardware ECC. */
	case NAND_CMD_READ1:
		column += 256;

	/* fall-through */
	case NAND_CMD_READ0:
		vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
		     " 0x%x, column: 0x%x.\n", page_addr, column);

		out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
		set_addr(ctrl, 0, page_addr, 0);

		ctrl->read_bytes = NAND_PAGE_SIZE + NAND_OOB_SIZE;
		ctrl->index += column;

		fsl_elbc_do_read(ctrl, 0);
		fsl_elbc_run_command(ctrl);
		return;

	/* READOOB reads only the OOB because no ECC is performed. */
	case NAND_CMD_READOOB:
		vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
		     " 0x%x, column: 0x%x.\n", page_addr, column);

		out_be32(&lbc->fbcr, NAND_OOB_SIZE - column);
		set_addr(ctrl, column, page_addr, 1);

		ctrl->read_bytes = NAND_PAGE_SIZE + NAND_OOB_SIZE;

		fsl_elbc_do_read(ctrl, 1);
		fsl_elbc_run_command(ctrl);
		return;

	/* READID must read all 5 possible bytes while CEB is active */
	case NAND_CMD_READID:
		vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n");

		out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
				    (FIR_OP_UA  << FIR_OP1_SHIFT) |
				    (FIR_OP_RBW << FIR_OP2_SHIFT));
		out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
		/* 5 bytes for manuf, device and exts */
		out_be32(&lbc->fbcr, 5);
		ctrl->read_bytes = 5;
		ctrl->use_mdr = 1;
		ctrl->mdr = 0;

		set_addr(ctrl, 0, 0, 0);
		fsl_elbc_run_command(ctrl);
		return;

	/* ERASE1 stores the block and page address */
	case NAND_CMD_ERASE1:
		vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
		     "page_addr: 0x%x.\n", page_addr);
		set_addr(ctrl, 0, page_addr, 0);
		return;

	/* ERASE2 uses the block and page address from ERASE1 */
	case NAND_CMD_ERASE2:
		vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");

		out_be32(&lbc->fir,
			 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
			 (FIR_OP_PA  << FIR_OP1_SHIFT) |
			 (FIR_OP_CM1 << FIR_OP2_SHIFT));

		out_be32(&lbc->fcr,
			 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
			 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));

		out_be32(&lbc->fbcr, 0);
		ctrl->read_bytes = 0;

		fsl_elbc_run_command(ctrl);
		return;

	/* SEQIN sets up the addr buffer and all registers except the length */
	case NAND_CMD_SEQIN: {
		unsigned int fcr;
		vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
		     "page_addr: 0x%x, column: 0x%x.\n",
		     page_addr, column);

		ctrl->column = column;
		ctrl->oob = 0;

		if (NAND_LARGE_PAGE) {
			fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
			      (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);

			out_be32(&lbc->fir,
				 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
				 (FIR_OP_CA  << FIR_OP1_SHIFT) |
				 (FIR_OP_PA  << FIR_OP2_SHIFT) |
				 (FIR_OP_WB  << FIR_OP3_SHIFT) |
				 (FIR_OP_CW1 << FIR_OP4_SHIFT));
		} else {
			fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
			      (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);

			out_be32(&lbc->fir,
				 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
				 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
				 (FIR_OP_CA  << FIR_OP2_SHIFT) |
				 (FIR_OP_PA  << FIR_OP3_SHIFT) |
				 (FIR_OP_WB  << FIR_OP4_SHIFT) |
				 (FIR_OP_CW1 << FIR_OP5_SHIFT));

			if (column >= NAND_PAGE_SIZE) {
				/* OOB area --> READOOB */
				column -= NAND_PAGE_SIZE;
				fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
				ctrl->oob = 1;
			} else if (column < 256) {
				/* First 256 bytes --> READ0 */
				fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
			} else {
				/* Second 256 bytes --> READ1 */
				fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
			}
		}

		out_be32(&lbc->fcr, fcr);
		set_addr(ctrl, column, page_addr, ctrl->oob);
		return;
	}

	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
	case NAND_CMD_PAGEPROG: {
		int full_page;
		vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
		     "writing %d bytes.\n", ctrl->index);

		/* if the write did not start at 0 or is not a full page
		 * then set the exact length, otherwise use a full page
		 * write so the HW generates the ECC.
		 */
		if (ctrl->oob || ctrl->column != 0 ||
		    ctrl->index != NAND_PAGE_SIZE + NAND_OOB_SIZE) {
			out_be32(&lbc->fbcr, ctrl->index);
			full_page = 0;
		} else {
			out_be32(&lbc->fbcr, 0);
			full_page = 1;
		}

		fsl_elbc_run_command(ctrl);

		/* Read back the page in order to fill in the ECC for the
		 * caller.  Is this really needed?
		 */
		if (full_page && ctrl->oob_poi) {
			out_be32(&lbc->fbcr, 3);
			set_addr(ctrl, 6, page_addr, 1);

			ctrl->read_bytes = NAND_PAGE_SIZE + 9;

			fsl_elbc_do_read(ctrl, 1);
			fsl_elbc_run_command(ctrl);

			memcpy(ctrl->oob_poi + 6,
				      (unsigned char *)&ctrl->addr[ctrl->index], 3);
			ctrl->index += 3;
		}

		return;
	}

	/* CMD_STATUS must read the status byte while CEB is active */
	/* Note - it does not wait for the ready line */
	case NAND_CMD_STATUS:
		out_be32(&lbc->fir,
			 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
			 (FIR_OP_RBW << FIR_OP1_SHIFT));
		out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
		out_be32(&lbc->fbcr, 1);
		set_addr(ctrl, 0, 0, 0);
		ctrl->read_bytes = 1;

		fsl_elbc_run_command(ctrl);

		/* The chip always seems to report that it is
		 * write-protected, even when it is not.
		 */
		out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
		return;

	/* RESET without waiting for the ready line */
	case NAND_CMD_RESET:
		dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
		out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
		out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
		fsl_elbc_run_command(ctrl);
		return;

	default:
		dbg("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
			command);
	}
}


/*
 * Write buf to the FCM Controller Data Buffer
 */
static void fsl_elbc_write_buf(struct fsl_elbc_ctrl *ctrl, const unsigned char *buf, int len)
{
	unsigned int bufsize = NAND_PAGE_SIZE + NAND_OOB_SIZE;

	if (len <= 0) {
		printf("write_buf of %d bytes", len);
		ctrl->status = 0;
		return;
	}

	if ((unsigned int)len > bufsize - ctrl->index) {
		printf("write_buf beyond end of buffer "
		       "(%d requested, %u available)\n",
		       len, bufsize - ctrl->index);
		len = bufsize - ctrl->index;
	}

	memcpy((unsigned char *)&ctrl->addr[ctrl->index], buf, len);
	/*
	 * This is workaround for the weird elbc hangs during nand write,
	 * Scott Wood says: "...perhaps difference in how long it takes a
	 * write to make it through the localbus compared to a write to IMMR
	 * is causing problems, and sync isn't helping for some reason."
	 * Reading back the last byte helps though.
	 */
	in_8(&ctrl->addr[ctrl->index] + len - 1);

	ctrl->index += len;
}

/*
 * read a byte from either the FCM hardware buffer if it has any data left
 * otherwise issue a command to read a single byte.
 */
static unsigned char fsl_elbc_read_byte(struct fsl_elbc_ctrl *ctrl)
{
	/* If there are still bytes in the FCM, then use the next byte. */
	if (ctrl->index < ctrl->read_bytes)
		return in_8(&ctrl->addr[ctrl->index++]);

	printf("read_byte beyond end of buffer\n");
	return ERR_BYTE;
}

/*
 * Read from the FCM Controller Data Buffer
 */
static void fsl_elbc_read_buf(struct fsl_elbc_ctrl *ctrl, unsigned char *buf, int len)
{
	int avail;

	if (len < 0)
		return;

	avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
	memcpy(buf, (unsigned char *)&ctrl->addr[ctrl->index], avail);
	ctrl->index += avail;

	if (len > avail)
		printf("read_buf beyond end of buffer "
		       "(%d requested, %d available)\n",
		       len, avail);
}


/* This function is called after Program and Erase Operations to
 * check for success or failure.
 */
static int fsl_elbc_wait(struct fsl_elbc_ctrl *ctrl)
{
	volatile lbus83xx_t *lbc = ctrl->regs;

	if (ctrl->status != LTESR_CC)
		return NAND_STATUS_FAIL;

	/* Use READ_STATUS command, but wait for the device to be ready */
	ctrl->use_mdr = 0;
	out_be32(&lbc->fir,
		 (FIR_OP_CW0 << FIR_OP0_SHIFT) |
		 (FIR_OP_RBW << FIR_OP1_SHIFT));
	out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
	out_be32(&lbc->fbcr, 1);
	set_addr(ctrl, 0, 0, 0);
	ctrl->read_bytes = 1;

	fsl_elbc_run_command(ctrl);

	if (ctrl->status != LTESR_CC)
		return NAND_STATUS_FAIL;

	/* The chip always seems to report that it is
	 * write-protected, even when it is not.
	 */
	out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
	return fsl_elbc_read_byte(ctrl);
}

static int fsl_elbc_read_page(struct fsl_elbc_ctrl *ctrl)
{
	fsl_elbc_read_buf(ctrl, ctrl->data_poi, NAND_PAGE_SIZE);
	fsl_elbc_read_buf(ctrl, ctrl->oob_poi, NAND_OOB_SIZE);

	if (fsl_elbc_wait(ctrl) & NAND_STATUS_FAIL)
		return -1;

	return 0;
}

/* ECC will be calculated automatically, and errors will be detected in
 * waitfunc.
 */
static void fsl_elbc_write_page(struct fsl_elbc_ctrl *ctrl)
{
	fsl_elbc_write_buf(ctrl, ctrl->data_poi, NAND_PAGE_SIZE);
	fsl_elbc_write_buf(ctrl, ctrl->oob_poi, NAND_OOB_SIZE);
}


static int fsl_elbc_ctrl_init(void)
{
	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
	elbc_ctrl.regs = &im->im_lbc;;

	/* clear event registers */
	out_be32(&elbc_ctrl.regs->ltesr, LTESR_NAND_MASK);
	out_be32(&elbc_ctrl.regs->lteatr, 0);

	/* Enable interrupts for any detected events */
	out_be32(&elbc_ctrl.regs->lteir, LTESR_NAND_MASK);

	elbc_ctrl.page = 0;
	elbc_ctrl.read_bytes = 0;
	elbc_ctrl.column = 0;
	elbc_ctrl.index = 0;
	elbc_ctrl.status = 0;
	elbc_ctrl.mdr = 0;
	elbc_ctrl.use_mdr = 0;
	elbc_ctrl.oob = 0;
	elbc_ctrl.addr = NULL;

	elbc_ctrl.oob_poi = malloc(NAND_OOB_SIZE);
	elbc_ctrl.data_poi = malloc(NAND_PAGE_SIZE);
	if (!elbc_ctrl.oob_poi || !elbc_ctrl.data_poi) {
		printf("elbc_ctrl init memory buffer failed\n");
		return -1;
	}

	return 0;
}

int fsl_nand_init(void)
{
	return fsl_elbc_ctrl_init();
}


void fsl_nand_buf_dump(unsigned char *buff, int len)
{
	int i = 0;

	for (i = 0; i < len; i++) {
		if (i%16 == 0)
			printf("\r\n 0x%08x:   ", ((int)buff + i));
		printf(" %02x", *(buff + i));
	}
	printf("\r\n");
}


int fsl_nand_reset(void)
{
	int ret = 0;

	fsl_elbc_cmdfunc(&elbc_ctrl, NAND_CMD_RESET,0,0);
	ret = fsl_elbc_run_command(&elbc_ctrl);

	return ret;
}


int fsl_nand_read_status(void)
{
	int ret = 0;

	fsl_elbc_cmdfunc(&elbc_ctrl, NAND_CMD_STATUS,0,0);

	dbg("\r\n%s: 0x%x.\r\n", __FUNCTION__, elbc_ctrl.mdr);
	return ret;
}

int fsl_nand_read_id(unsigned char *makerCode, unsigned char *deviceCode)
{
	int ret = 0;
	unsigned char id[5];

	memset(id,0x00,5);

	fsl_elbc_cmdfunc(&elbc_ctrl, NAND_CMD_READID,0,0);
	fsl_elbc_read_buf(&elbc_ctrl, id, 5);

	*makerCode = id[0];
	*deviceCode = id[1];

	return ret;
}

int fsl_nand_erase_block(int block)
{
	int ret = 0;

	fsl_elbc_cmdfunc(&elbc_ctrl, NAND_CMD_ERASE1, -1, block*NAND_PAGES_PER_BLOCK);
	fsl_elbc_cmdfunc(&elbc_ctrl, NAND_CMD_ERASE2, -1, -1);

	return ret;
}


int fsl_nand_read_page(int page, unsigned char *data, int data_len, unsigned char *oob, int oob_len)
{
	int ret = 0;

	fsl_elbc_cmdfunc(&elbc_ctrl, NAND_CMD_READ0, 0x00, page);
	fsl_elbc_read_page(&elbc_ctrl);

	if (data)
	{
		memcpy(data, elbc_ctrl.data_poi, data_len);
	}
	if (oob)
	{
		memcpy(oob, elbc_ctrl.oob_poi, oob_len);
	}

	return ret;
}


int fsl_nand_write_page(int page, unsigned char *data, int data_len, unsigned char *oob, int oob_len)
{
	int ret = 0;

	if (data)
	{
		memcpy(elbc_ctrl.data_poi, data, data_len);
	}
	if (oob)
	{
		memcpy(elbc_ctrl.oob_poi, oob, oob_len);
	}

	fsl_elbc_cmdfunc(&elbc_ctrl, NAND_CMD_SEQIN, 0x00, page);
	fsl_elbc_write_page(&elbc_ctrl);
	fsl_elbc_cmdfunc(&elbc_ctrl, NAND_CMD_PAGEPROG, 0x00, page);

	return ret;
}

int fsl_nand_chip_erase(void)
{
	int i = 0;

	for (i = 0; i < (NAND_CHIP_SIZE/NAND_BLOCK_SIZE); i++)
	{
		fsl_nand_erase_block(i);
	}

	return 0;
}

int fsl_nand_chip_scan(void)
{
	int block = 0;
	int invalid = 0;
	char oob[NAND_OOB_SIZE];

	memset(oob, 0, NAND_OOB_SIZE);

	for (block = 0; block < (NAND_CHIP_SIZE/NAND_BLOCK_SIZE); block++)
	{
		fsl_nand_read_page(block*NAND_PAGES_PER_BLOCK,
					NULL, 0,
					oob, NAND_OOB_SIZE);
		if (0xFF != oob[0])
		{
			invalid = 1;
		}
		fsl_nand_read_page(block*NAND_PAGES_PER_BLOCK +1,
					NULL, 0,
					oob, NAND_OOB_SIZE);
		if (0xFF != oob[0])
		{
			invalid = 1;
		}
		if (invalid)
		{
			printf("\r\nblock %d is invalid!\r\n", block);
		}
	}

	return 0;
}


